The goal of this course is to give up to date knowledge about the power of SpecMan and how to write and understand “E” programming. The course assumes basic knowledge in VLSI coding, whether it is for design or verification. The course will go over SpecMan commands, explain the syntax of the “E” language, teach the most advance verification techniques using that tool, and explain the methodology to write good “E” code. The course will also give real practice in writing an effective “E” code. The labs will give examples, and require work in planning, developing and using verification “E” code. Graduates of this course are expected to know how to develop the basic SpecMan verification environment, how to understand the advanced verification concepts, and no less important – show basic knowledge in SpecMan in job interviews.
Who can attend
Any SW/HW engineer or practical engineer
Studies: 5 meetings, those with good knowledge in System Verilog can skip the first meeting
One evening class on weekdays (Mon-Thu, 17:30pm-22.00pm) or one morning class on Friday (9.00-13:30).
20 people max
The course will be done twice a week for 2.5 weeks
Course Grading Criteria
Course exam and home exercises
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