הסכימה היא מסמך השליטה בכל תכנון מעגלים מודפסים.(PCB)  היא מרכזת את כל כוונת התכנון ומניעה את כל התהליכים במורד הזרם, כולל סימולציה, ניתוח, פריסה, ייצור והרכבה. ככזו, קריטי שהסכימה תשקף במדויק את הדרישות והמפרטים האלקטרוניים של המוצר.

מבחינה היסטורית, המשימה החשובה ביותר היא לוודא שכוונת התכנון הסכימטית הועברה כראוי ובוצעה בדרך כלל בגיליון אחד או בבלוק אחד בכל פעם באופן ידני, עם קצת אוטומציה כדי לסייע בתהליך-כגון ייצוא של כל החומרים לקבצי טקסט או גיליונות אלקטרוניים.

עם זאת, תכנוני המעגלים של היום הופכים יותר ויותר מורכבים והאימות הידני דורש זמן רב. יתרה מכך, האימות הידני של מעגל מורכב מהווה סיכון משמעותי בכך שאינו מזהה טעויות תכנון סכימטיות המועברות, בתורן, לתהליכים במורד הזרם ולבסוף ללוח המיוצר. כתוצאה מכך, הם גורמים לעלות יקרה ומגדילים את זמן ההגעה לשוק. ככל שמתגלה שגיאה מאוחר יותר במחזור התכנון, כך התיקון יעלה יותר, במיוחד אם אב הטיפוס או המוצר נבנה פיזית.

התרשימים של היום פשוט מסובכים מכדי לבצע אימות ידני באופן אמין. במחקר שנערך לאחרונה על ידי קבוצת אברדין %65 מהחברות שנבדקו ציינו כי מורכבות המוצר ההולכת וגוברת היא אתגר התכנון העליון שלהם בתכנון מעגלים מודפסים (איור 1) .

איור 1: אתגרים מובילים בתכנון PCB מקור: קבוצת אברדין.

הממצאים של קבוצת אברדין מחזקים את הביקורתיות של הבטחת התכנון הסכימטי ללא טעויות לאורך כל תהליך פיתוח המוצר. מאמר זה דן באתגר כיצד תהליך סקירה סכימטי יעיל ואוטומטי לחלוטין יכול למנוע טעויות בתכנון סכימטי, ובכך להפחית עלויות יקרות ולשפר את הזמן ההגעה לשוק.

סקירה סכימטית ידנית – כבר לא אופציה

לכידה סכימטית היא בהחלט לא המשימה המרגשת או הזוהרת ביותר בתהליך פיתוח המוצר. למעשה, מהנדסי חומרה רבים מאצילים את המשימה לטכנאים בתוך הצוות, ומספקים שרטוטים ידניים או ייצוגי PowerPoint של המעגל לטכנאי כדי שידע מה לעשות. השגה זו מאפשרת למהנדס החומרה להתמקד במשימות אחרות, כגון אופטימיזציה של מעגלים או בדיקות מעבדה, אך היא גם מגבירה את החשיבות של אימות נכון והבטחה שהסכימה מומשה כראוי.

כשם שלא ניתן לבנות בניין גדול על בסיס חלש, לא ניתן לתכנן מוצר נהדר על תכנון סכימטי חלש. ככל שמורכבות התכנון גוברת וזמן פיתוח המוצר מתקצר, הצורך באימות סכימטי אוטומטי מלא הופך להיות חשוב יותר. ללא אימות סכימטי מתאים, קיים פוטנציאל משמעותי לבעיות חומרה נוספות, לזמן איטי יותר בהגעה לשוק, בהגדלת עליות התכנון ובאיכות מוצר ירודה (איור 2).

איור 2: השפעת אימות סכימטי גרוע ככל שמורכבות התכנון עולה.

במהלך סקירה סכימטית ידנית, צוותים מתמקדים בדרך כלל רק בנושאי התכנון הנפוצים ביותר, כולל:

•  רכיבים שאינם מחוברים כראוי לחשמל ו/או לקרקע

•  מחסור במתח

•  דיודות מכוונות בצורה לא נכונה

•  רשת מקלט חסרה

 • אי התאמת מתח פינים (ספי מתח שונים(

 • מחברי לוחות שגויים

 • בעיות קטנות וכתוצאה מכך עיכובים, עלות וסיכון מיותרים

אמנם לא מדובר בנושאים מורכבים, אך קשה, אם לא בלתי אפשרי, למצוא באופן חזותי את כל המופעים של נושאים אלה בתכנון מורכב. ואלו רק הנושאים הסכימטיים הנפוצים ביותר. יש עוד הרבה בעיות פוטנציאליות שסקירה ידנית פשוטה לא יכולה למצוא.

 אימות סכימטי אוטומטי לחלוטין

כלי האימות (ECAD) התמקדו באופן היסטורי בפריסה ובהיבטים של הייצור ושל התכנון, לא בסכימטיות. בהתחשב בעובדה ש -%78 מכל הפרויקטים חווים שניים או יותר התאמות וכי ניתן לייחס את המקור למרבית הבעיות לשגיאות תכנון סכימטיות, הגיע הזמן להשתמש באימות סכימטי אוטומטי לחלוטין. ביטול שגיאות סכימטיות יכול לגרום לחסכון משמעותי בעלויות ובזמן, וכתוצאה מכך להביא לזמן הגעה לשוק מהיר יותר, לאיכות משופרת של המוצר משופרת ולהקטנת הסיכונים בתכנון (איור 3) .

 איור 3: השפעה של טעויות סכימטיות מופחתות.

על ידי אוטומציה מלאה של אימות סכימטי המתרחש במהלך הלכידה הסכימטית, ולא לאחר מכן, תהליך הפיתוח עובר שמאלה, וכתוצאה מכך מתקבלים יתרונות מוכחים, כגון הפחתת זמן מחזור, עלויות נמוכות יותר וסילוק ספיני תכנון (איור 4).

איור 4: טכנולוגיית משמרת שמאל.

באמצעות ניתוח תקינות סכימטית ע"י Xpedition מתוצרת- Siemens EDA (חלק מתוכנת התעשייה הדיגיטלית של סימנס), יכולים המהנדסים לבדוק באופן מלא את כל הרשתות בסכימה באמצעות בדיקות מוגדרות מראש וספריית רכיבי דגמים נרחבת וחכמה. הבדיקות מתבצעות במהירות במקביל ללכידה סכימטית, כך שהפריסה תצליח בסבירות הגבוהה ביותר כבר בנסיון הראשון.

יותר מ- 125 בדיקות של שלמות סכימטית קניינית של Xpedition הינן ממצות, מהירות ומודעות גם לכוח וגם לטכנולוגיה. הם נועדו לזהות גם שגיאות פרמטריות וגם שיטות תכנון לקויות, והם עובדות עם כל כלי התכנון העיקריים של ה- PCB .רמה זו של ניתוח סכימטי אוטומטי יכולה לחסוך לצוותי התכנון מאות שעות של בדיקה ויזואלית וזמן ניפוי במעבדה.

יש לנצל ניתוח סכימטי אוטומטי לאחר השלמת הסכימה הראשונית, כך שניתן לנתח כל רכיב ורשת באופן מלא. ניתן לעשות זאת לפני שתוכננה הפריסה הפיזית. דו"ח האימות שהתקבל מדגיש איזורי תכנון שיש לדון בהם במהלך סקירת תכנון צוות.

שילוב ניתוח התקינות הסכימטית עם Xpedition מקצר את הזמן הנדרש לסקירה סכימטית תוך הקלה על חייו של המתכנן. ניתן להריץ פרויקט ניתוח ישירות מהסכימה של Xpedition לתכנן מתחים מראש ולהגדיל באופן מיידי את תוצאות הניתוח מבלי לבצע חיפוש נוסף אחר הרשת או הרכיב. תכונות אלה מצמצמות את הזמן הדרוש לניווט בתוצאות ואיסוף נתוני פרויקטים ממקורות מרובים.

המאפיינים העיקריים של ניתוח תקינות סכימטית של Xpedition כוללים:

• 125 + בדיקות אוטומטיות מובנות
• 6+  מיליון דגמים חכמים
• תמיכה ביצירת דגמי מכשירים מותאמים אישית
• בדיקה מלאה של % 100 מהרשתות הסכימטיות
• תמיכה בניתוח קישוריות בין לוחות שונים
• התקנה קלה ותפעול אינטואיטיבי
• תוצאות אינטליגנטיות לאחר עיבוד ודיווח למעקב וביקורת
• תומכת בכל כלי ה- EDA העיקריים
• אין צורך בתשתיות נוספות

מערכת ניתוח תקינות סכימטית של Xpedition מבצעת בממוצע, 400,000 בדיקות לכל תכנון. דוגמה לתוצאות לאחר ביצוע ניתוח תקינות סכימטית של Xpedition על סכימטי מוצגות באיור 5.

איור 5: בדוגמה זו, מערכת ניתוח תקינות סכימטית של Xpedition מצאה 82 בעיות קריטיות ו -235 פגמים וסיפקה 84 אזהרות – הרבה יותר ממה שניתן היה למצוא באמצעות בדיקה ידנית.

ארבעה תחומים בהם מתרחשות טעויות הניתנות למניעה הן: סמלים וספריות, חיבורי רשת, דרישות רכיבים ותקשורת בין מתכננים. מערכת ניתוח תקינות סכימטית של Xpedition יכולה לעזור בכל אחד מהתחומים הללו. אם סמל אינו נכון, יופיע חיבור רשת שגוי, שיסומן על ידי הניתוח. ישנם סוגים רבים של בעיות בחיבור רשת, כגון פין חשמל שאינו מחובר לחשמל (איור 6) או קלט שחסר לו מנהל התקן.

איור 6: בעיות התכנון הקריטיות הנפוצות ביותר שדווחו על ידי סימנס ייעוץ בשנת 2020. אלו היו טעויות שהתגלו בעיצובים של לקוחות אמיתיים באמצעות ניתוח סכמטי. (בניכוי False positives and redundant results) .

יתר על כן, דרישות הרכיב מתבטאות במודלים של ניתוח סכימטי, כולל דרישות pull-up/pull-down  וכיצד יש להתייחס לפין כאשר היא אינו בשימוש. הפרות של כללים אלה מזוהות באופן אוטומטי. ניתוח סכימטי יכול גם לאפשר תקשורת טובה יותר בין מתכנים על ידי דרישה שהם יעבדו יחד כדי להבין את הסכימה ולנקות כל פרט מעורפל, דבר העשוי גם לדרוש תיעוד מסודר. באופן כללי, סוג זה של בדיקות אוטומטיות מהווה את הבסיס לשיטות תכנון טובות.

 סיכום

אחת המטרות העיקריות של כל צוות פיתוח מוצרים היא לצמצם את מספר הבעיות בתכנון לפני שמשחררים את המוצר לשוק. בהתחשב בעובדה שהסיבה העיקרית לבעיות תכנון היא לרוב טעויות תכנון סכימטיות, תהליך הכולל אימות סכימטי אוטומטי לחלוטין יכול להפחית באופן משמעותי את שכיחות הבעיה היקרה הזו. ניתוח תקינות סכימטית של מערכת Xpedition מאפשר בדיקה מלאה של כל הרשתות בסכימה באמצעות בדיקות מוגדרות מראש וספריית רכיבים נרחבת וחכמה.

באופן ספציפי, מערכת ניתוח תקינות סכימטית של Xpedition  מאפשרת:

 • אוטומציה של איתור טעויות תכנון קריטיות

•  מונעת %50 עד %70 ממשימות התכנון הנגרמות על ידי שגיאות סכימטיות ושוליות

 • מספקת את הביטחון כי כוונת התכנון מיושמות בפעם הראשונה

•  מבטלת שעות רבות של סקירה ידנית, מפחיתה סיכון ומספקת החזר השקעה מהיר עם הדרכה מינימלית

ניתן לדגום תכנונים חדשים ולנתח אותם כל הזמן על מנת להבטיח כי שינויי התכנון של הרגע האחרון מוערכים במלואם. ניתן לשלב גם נתונים מתכנונים מרובים כדי לבצע אימות ברמת המערכת. יתר על כן, ניתן לבצע ניתוח תקינות סכימטי על תכנונים גם לאחר שיצאו לשוק כדי לשפר את איכות התכנון האלקטרוני העתידי, להגדיל את התשואה ולהקטין את החזרת המוצרים.

התכנונים המורכבים של היום אינם מאפשרים עוד סקירה ואימות סכימטי ידני. מערכת ניתוח תקינות סכימטי של Xpedition מספקת אימות סכימטי אוטומטי לחלוטין במקביל ללכידה סכימטית. הטכנולוגיה הייחודית הזו מבטיחה בדיקה מלאה של כל הרשתות בסכימה, וכתוצאה מכך מבטיחה פחות ספינים תכנוניים ושיפור זמן ההגעה לשוק.

• ניקול קייל היא מהנדסת שיווק טכני העובדת בקבוצת מערכות ה- PCB של Siemens EDA.

הפוסט כיצד ניתן למנוע שגיאות תכנון סכימטיות באמצעות האימות האוטומטי של סימנס הופיע לראשונה ב-Chiportal.

The Xilinx Zynq UltraScale+ MPSoC represents the next generation of multicore platforms for compute-intensive, security and safety-related applications. The software and tools portfolio of Mentor Graphics provides developers with a single source for all their software needs. Engineering teams for Zynq UltraScale+ MPSoC can now develop and debug their advanced products under a single umbrella of licensing, support, inter-core communication and management, software integration, tools, and professional services.

“We are very excited that Mentor has chosen to support Zynq UltraScale+ MPSoC with its solutions,” stated Ramine Roane, senior director of Software Product Marketing, Xilinx Inc. “The combination of Xilinx Zynq UltraScale+ MPSoC and the Mentor Embedded portfolio of software and tools will allow system developers to more easily and quickly deploy complex system designs, allowing them to benefit from the high performance, lower system cost, reduced power consumption, and smaller foot print advantages that come with Zynq UltraScale+ MPSoC.”

The Xilinx Zynq UltraScale MPSoC offers a unique combination of ARM® Cortex®-A53 64-bit processors with hardware virtualization for the execution of compute-, bandwidth- and graphics-intensive applications: ARM dual Cortex-R5 processors for real-time and safety-critical applications; hard and soft acceleration engines; and on-chip programmable logic for user-defined task acceleration. Such capabilities are compelling enough that architects are now beginning to design Zynq UltraScale+ MPSoC into complex systems comprised of one or more Linux or RTOSes running on a hypervisor for the ARM Cortex -A53 cores, and RTOS or bare-metal environments executing on the ARM Cortex-R5 cores.

“We’ve been working closely with Xilinx on their embedded development ecosystem for the Zynq UltraScale+ MPSoC since we are a leader in heterogeneous multicore technology,” stated Scot Morrison, general manager of the platforms business unit, Mentor Graphics Embedded Systems Division. “Dealing with the complexities of today’s heterogeneous multicore systems, Xilinx customers can realize faster time to embedded development and system performance with minimized risk using our solution.”

Product Availablity

Mentor Graphics will be releasing various embedded development products to support the Zynq UltraScale+ MPSoC product within 2016. For additional product information, visit the product website at: www.mentor.com/embedded-software/semiconductors/xilinx.

About Mentor Embedded

The Mentor Graphics Embedded Systems Division enables embedded development for a variety of applications including automotive, industrial, smart energy, medical devices, and consumer electronics. Embedded developers can create systems with the latest processors and micro-controllers with commercially supported and customizable Linux-based solutions including the industry-leading Sourcery CodeBench and Mentor Embedded Linux products. For real-time systems, developers can take advantage of the small-foot-print and low-power-capable Nucleus RTOS. For more information, visit www.mentor.com/embedded

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year of approximately $1.18 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

(Mentor Graphics, Mentor and Nucleus are registered trademarks and Sourcery is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owner.) The registered trademark Linux® is used pursuant to a sublicense from LMI, the exclusive licensee of Linus Torvalds, owner of the mark on a world-wide basis.

הפוסט Mentor Graphics Announces Broad Embedded Product Portfolio Coverage for Xilinx Zyng UltraScale+MPSoC Platform הופיע לראשונה ב-Chiportal.

WILSONVILLE, Ore., June 1, 2016—Mentor Graphics Corporation (NASDAQ: MENT) today announced that customers and ecosystem partners are expanding their use of Calibre Pattern Matching solution to overcome previously intractable IC verification and manufacturing problems. The solution is integrated into the Mentor® Calibre nmPlatform solution, creating a synergy that drives these new applications at IC design companies and foundries, across multiple process nodes.

Calibre Pattern Matching technology supplements multi-operational text-based design rules with an automated visual geometry capture and compare process. This visual approach is both very powerful in its ability to capture complex pattern relationships, and to work within mixed tool flows, making it much easier for Mentor customers to create new applications to solve difficult problems. Because it is integrated into the Calibre nmPlatform toolset, the Calibre Pattern Matching functionality can leverage the industry-leading performance and accuracy of all Calibre tools and flows to create new opportunities for design-rule checking (DRC), reliability checking, DFM, yield enhancement, and failure analysis.

“Our customers count on eSilicon’s design services, IP, and ecosystem management to help them succeed in delivering market-leading ICs,” said Deepak Sabharwal, general manager, IP products & services at eSilicon. “We use Calibre Pattern Matching to create and apply a Calibre-based yield-detractor design kit that helps identify and eliminate design patterns that impact production ramp-up time.”

Since its introduction, use models for Calibre Pattern Matching technology have rapidly expanded, solving problems that were previously too complex or time-consuming to be implemented. New use cases include the following:

• Physical verification of IC designs with curved structures—for analog, high-power, radio frequency (RF) and microelectromechanical (MEMS) circuitry—is extremely difficult with products designed to work with rectilinear design data. Calibre customers are automating that verification using a combination of Calibre Pattern Matching technology and other Calibre tools for much greater efficiency and accuracy, especially when compared to manual techniques.

• Calibre Pattern Matching technology can be used to quickly locate and remove design patterns that are known or suspected of being difficult to manufacture (“yield detractors”). Foundries or design companies create libraries of yield detractor patterns that are specific to a process node or a particular design methodology. Samsung Foundry used this approach in its Closed-Loop DFM solution to help its customers ramp to volume faster, and reduce process-design variability.

• Some customers use Calibre Pattern Matching technology with Calibre Auto-Waivers functionality to define a specific context for waiving a DRC violation. This enhancement allows for automatic filtering of those violations for significant time savings and improved design quality.

“To help our customers create manufacturing-ready designs, we use Calibre Pattern Matching to create and use a yield detractor database to fix most of the litho hotspots in the block level. Then we perform fast signoff DFM litho checking at the chip level using an integrated solution with Calibre Pattern Matching and Calibre LFD” said Min-Hwa Chi, senior vice president, SMIC. “By offering a solution for manufacturability robustness that is built on the Calibre platform, we are seeing ready customer adoption of SMIC’s DFM solution.”

With the Calibre Pattern Matching tool, design companies can now optimize their physical verification checking to their unique design styles. The tool is easy to adopt because it doesn't rely on expertise in scripting languages. Instead, any engineer can readily define a visual pattern that captures the designer's expertise in the critical geometries and context for that configuration. “With the growing adoption of Calibre Pattern Matching technology, Mentor continues to help our customers address increasing design complexity, regardless of the process node they are targeting,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “By incorporating the Calibre Pattern Matching tool, the Calibre platform becomes an even more valuable bridge between design and manufacturing for the ecosystem.”

At the 2016 Design Automation Conference, Mentor has a Calibre Pattern Matching presentation on Tuesday, June 7 at 3PM in the Mentor booth #949. Register for the session using the registration form https://www.mentor.com/events/design-automation-conference/schedule

Samsung Foundry Closed-Loop DFM Solution Leverages Mentor Graphics Tools to Accelerate Customer Yield Ramps

WILSONVILLE, Ore., June 1, 2016—Mentor Graphics Corp. (NASDAQ: MENT) today announced that Samsung Foundry’s Closed-Loop DFM solution uses production Mentor Calibre and Tessent platforms to accelerate customer yield ramps. A successful yield ramp directly impacts customer product cost and time-to-market. In the Closed-Loop DFM flows, Samsung integrates its comprehensive DFM kits with its testing and manufacturing expertise to identify integrated circuit (IC) design patterns that are most likely to impact manufacturing yield, thereby helping customers improve design quality, yield, and ramp to production. The Samsung solution extracts customer yield-averse design patterns, feeds that information forward to optimize manufacturing and testing, and closes the loop with feedback from silicon results for product design and yield improvement. This solution is not only useful to initial customer designs, but it also allows learnings from current production designs to be applied to next-generation designs from that same customer across entire product families.

“Samsung is committed to helping our customers to ramp up as quickly as possible and get to market faster with their semiconductor designs,” said JaeHong Park, senior vice president, Design Services, Samsung Foundry. “Our Closed-Loop DFM solution, which is built on top of Mentor platforms, gives our customers deeper, faster insight into design hotspots, improving quality and yield. Our work has shown more than 10 percent product yield gains in the initial phase of production when compared to the same design without our Closed-Loop DFM system applied.”

“This new use model for the Calibre and Tessent platforms is another milestone in our continued partnership with Samsung,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “Our joint customers can use Closed-Loop DFM with production Calibre and Tessent software to deliver leading-edge products faster on all of Samsung’s process nodes.”

The pre-manufacturing flow in Closed-Loop DFM, called PRISM (Pattern Recognition & Identity Scoring Method), analyzes an IC design by deconstructing it into layout patterns and, using the Calibre Pattern Matching solution, identifying patterns known to have been yield detractors in the past. Samsung then uses Calibre LFD software along with other Calibre DFM products to spot previously unknown potential lithography hotspots and analyze their likely impacts on manufacturability. Samsung and the customer jointly make the best use of PRISM results to determine design and/or manufacturing changes needed to ensure that the customer’s unique design style achieves target yields and reduces production ramp variability.

After manufacturing, a second Closed-Loop DFM flow called FLARE (Failure anaLysis And yield Rank Estimation with DFM hotspot database) identifies yield-limiting layout patterns based on silicon results. Fail data from wafer test are diagnosed by the Foundry customer and analyzed by Samsung Foundry to identify unique layout patterns that cause yield loss. Samsung and its customers use this information to analyze systematic issues caused by physical design features to improve the ramp-up speed for design re-spins, as well as for new designs using the same IP blocks and or subsystems. Samsung Foundry also uses FLARE data to improve its DFM kits to share silicon findings with customer designers. FLARE uses the Tessent Diagnosis tool for layout-aware diagnosis, the Calibre Pattern Matching solution for generating a hotspot database, and statistical analysis in the Tessent YieldInsight® product to identify the yield limiting layout patterns.

The Closed-Loop DFM flows are in production use today for customers of Samsung Foundry services. While proven in 14 nm technology, the flows can be used for ICs manufactured with other Samsung process nodes.

At the 2016 Design Automation Conference, Mentor and Samsung are co-hosting a lunch seminar entitled “Accelerate Yield Ramps with Samsung Foundry Closed-Loop DFM and Mentor Tools.” The event is Monday, June 6, from 12:00 to 1:30 PM. Interested customers can register for the event using this registration link https://www.mentor.com/products/ic_nanometer_design/events/samsung-dac-lunch-seminar

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year of approximately $1.18 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Web site: http://www.mentor.com.

הפוסט Samsung DFM and Mentor Calibre Pattern Matchin הופיע לראשונה ב-Chiportal.

New HA1000 System Tests ICs for High-Growth Applications Including Mobile Electronics and High-Performance Networking

Munich, Germany, 01.06.2016 – Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) has introduced its HA1000 die-level handler, a cost-efficient test solution for determining known good dies (KGD) prior to IC packaging.

Economics is a driving factor in die-level testing. Determining a semiconductor device’s viability prior to packaging or building memory stacks is critical to avoiding rework, achieving high yields and lowering costs. Performing pre-assembly testing of singulated devices provides a new level of visibility into the quality of the device prior to committing additional devices and expensive packages to an assembly which could potentially have to be scrapped because of undetected problems. Advantest’s new die level handler allows full device testing to be performed before assembly, providing time-critical information that today is typically only available at final test.

“Testing and debugging today’s 2.5D, 3D and fine-pitch chip-scale-package devices require a KGD approach capable of testing the ICs while they are still in die form,” said Zoë Conroy, manager, Silicon Test and Product Engineering, Technology and Quality, Supply Chain Operations of Cisco Corporation. “Using the HA1000 to do KGD testing has enabled a faster time-to-market, lowering the overall product cost.”

Koichi Tsukui, senior vice president at Advantest Corporation commented, “We have leveraged knowledge stemming from decades of experience in device handling and thermal control technology to develop this new class of die-level-handlers. Our customers can now precisely position and probe singulated devices after they have been bumped, thinned and sawed. They will realize improved yields at final assembly, and that is an important achievement.”

Advantest’s HA1000 is designed to handle a wide variety of devices from large high-power server/GPU type devices to small system-on-chips (SoCs) and memory devices/stacks, such as HBM2. The die-level-handler can handle thick parts and thin parts as well as stacks of 3D devices and partially or fully assembled 2.5D integrations. In addition, the HA1000 is ideal to probe fine-pitch pads, bumps, microbumps and pillars. Future applications of the system may also include the probing of Through-Silicon-Vias (TSVs).

The handler employs a precision vision alignment system capable of precisely positioning probe points to the finest pitch in use today. While properly positioning the chuck under the probes, the system can also adjust the planarity to match with the device surface to insure a solid device connection.

An active thermal control (ATC) system enables the HA1000 to adjust on the fly to temperature fluctuations at the die’s surface over a very broad dynamic range of -40˚ C to 125˚ C. The temperature of the thermal head quickly responds using a hot-cold fluid mix. Thanks to low thermal resistance and high thermal capacity the system can handle high power devices with a thermal responsiveness which is often better than is possible in a packaged environment. This allows manufactures to test parts at higher power levels and/or tighter margins which can improve yields while reducing scrap.

.Production units of the new HA1000system have already begun shipping

About Advantest

A world-class technology company, Advantest is a leading producer of automatic test equipment (ATE) for the semiconductor industry and a premier manufacturer of measuring instruments used in the design and production of electronic instruments and systems. Its leading-edge systems and products are integrated into the most advanced semiconductor production lines in the world. The company also focuses on R&D for emerging markets that benefit from advancements in nanotech and terahertz technologies, and has introduced multi-vision metrology scanning electron microscopes essential to photomask manufacturing, as well as a groundbreaking 3D imaging and analysis tool. Founded in Tokyo in 1954, Advantest established its first subsidiary in 1982, in the USA, and now has subsidiaries worldwide. More information is available at www.advantest.de .

For further information please contact:

Corporate Communications
Email: info@eu.advantest.com

הפוסט Advantest Launches New Die-Level Handling System Enabling KGD Test Strategy Required for Memory, Large High-Power, and Advanced 2.5D and 3D Semiconductors הופיע לראשונה ב-Chiportal.

Mentor Graphics Corporation (NASDAQ: MENT), the market and technology leader in printed circuit board (PCB) design solutions, today announced its newest offering and key building block in the Xpedition® platform, the Xpedition Systems Designer product for multi-board systems connectivity. The Xpedition Systems Designer product captures the hardware description of multi-board systems, from logical system definition down to the individual PCBs, automating multi-level system design synchronization processes to ensure team collaboration with accuracy and faster design productivity.

Current systems design processes for advanced electronics are fraught with multiple, disconnected tools used for system definition, with no standard methodology to synchronize and transfer design data between design disciplines and abstraction levels. This results in incorrect electrical connections, mechanical interference, and the high costs of manual synchronization.. The Xpedition Systems Designer product resolves this problem as the industry’s only single, integrated, and automated methodology that captures complete logic system definitions. The system may consist of multiple boards, cables and other system elements, such as backplane, cable assemblies, sensors and actuators. This solution enables consistency and completeness of the multi-board system description. “Systems design involves collaboration across disciplines, and is critical to modern product development. Traditional design practices isolate systems capture from the rest of the process, lowering team productivity, stifling innovation, and increasing product cost,” stated John MacKrell, vice president, Systems Engineering Knowledge Council lead of CIMdata. “Mentor Graphics’ new systems design technology enables engineering teams to capture system designs, while collaborating effectively with all those involved in the design and implementation process to optimize the end product.”

The Industry’s Only “Common Cockpit” for System-wide Design Connectivity The Xpedition Systems Designer product replaces time- and resource-consuming manual processes and the redundant re-entry of data with automatic synchronization of design changes across multiple levels and disciplines. This unique design “cockpit” enables system-wide partitioning of logical system blocks into individual PCBs. The environment fully supports concurrent design, enabling team members to simultaneously engineer and collaborate on different components of the system.

“Our new Xpedition platform delivers ‘industry-first’ technologies and our new Systems Designer product is a clear example,” stated Henry Potts, vice president and general manager of Mentor Graphics Systems Design Division. “Xpedition Systems Designer was developed as the industry’s best environment for design connectivity and team collaboration to deliver consistency of design integrity across disparate domains, tools and individuals.

” Xpedition Systems Designer – Key Features and Benefits The Xpedition Systems Designer product provides a broad range of capabilities to ensure accurate, concurrent, and reliable systems design connectivity via automated processes. Here is a list of added functionality to optimize systems design efficiency:

• Single cockpit for logical system definition: System-level blocks and intra-board connectivity are defined within a common environment. System architectures created in Visio can by imported to accelerate system capture. Advanced synchronization work-in-progress design data enables multiple engineers to concurrently collaborate on the logical system level, as well as within the lower-level PCB projects.

• Simplified system-wide partitioning: A system can be easily partitioned into multiple board projects and associated connectivity. Automated connectivity synchronizes changes across the system, enabling ‘what-if’ re-partitioning exercises to optimize the system for performance, size and cost.

• Correct-by-design connector management: The effort to add, manipulate and update connectors is simplified with on-the-fly creation of parameterized connectors. Automated connector mating and pin pairing, as well as synchronization between PCB projects and system design data, eliminates connector errors throughout the design cycle.

• Automated connectivity definition and verification: Definition of connections between system elements including connection order and wiring of multiple nets and wires is highly automated. Signals can be traced across the entire system to ensure that the connectivity is as specified. The Xpedition Systems Designer product will be available in December 2014.

הפוסט Mentor Graphics Announces Xpedition System Designer for Comprehensive Multi-board Systems Development הופיע לראשונה ב-Chiportal.

"Embedded non-volatile memories are becoming an increasingly important part of SoC designs created by our key customers," notes Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Kilopass' support for this technology at the 16FinFET node enables us to offer our mutual customers a complete solution that saves design time, chip area and power consumption."

The Kilopass OTP 2T bit cell continues to be easily manufactured and demonstrates the high level of reliability and performance similar to results produced at other process geometries built with planar transistor structures. Kilopass' OTP 2T bit cell technology can scale easily from 180nm to 28nm and beyond across a wide variety of process technologies including low power, high-voltage, and high-K metal gate.

As TSMC process migrates to FinFET transistor structures, Kilopass' antifuse OTP NVM was successfully ported to the FinFET process. The solution provided will also cover the methodology that meets the challenges of OTP NVM memory IP design for FinFET technology to enable faster time to market with high quality and reliability for TSMC and Kilopass' joint customers.

הפוסט TSMC, Kilopass Deliver NVM OTP IP for the 16FinFET Process Node הופיע לראשונה ב-Chiportal.

הפוסט New ARC HS38 Processor Delivers Twice the Performance for Embedded Linux Applications הופיע לראשונה ב-Chiportal.

The D2692 is a Dual UART Core software compatible with the SC26C92, SCC2692 and SCN2681. But on the contrary to it, DCD’s IP Core offers additional features and deeper FIFOs, like 8 character receiver, 8 character transmit FIFOs, watch dog timer for each receiver, mode register 0, extended baud rate, programmable receiver and transmitter interrupts.  

Bytom, 5^th of September 2013. The D2692 Dual Universal Asynchronous Receiver/Transmitter is a communication device that provides two full-duplex asynchronous receiver/transmitter channels in just one single package. DCD’s IP Core interfaces directly with microprocessors and may be used in a polled or interrupt driven system, furthermore provides modem and DMA interface. The operating mode and data format of each channel can be programmed independently. – Additionally, each receiver and transmitter can select its operating speed – says Jacek Hanke, DCD’s CEO – as one of 27 fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The opportunity to program independently the operating speed of the receiver and transmitter, denotes the UART particularly attractive for dual-speed channel applications like eg clustered terminal systems.

Every receiver is being equipped with fifo to minimize the potential of receiver over-run and to reduce interrupt overhead in interrupt driven systems. Moreover, the D2692 UART IP Core ensures a flow control capability, to disable a remote DUART transmitter, when the receiver buffer is full. To make this design even more functional, there’ve been added multipurpose 7-bit input port and a multipurpose 8-bit output port. They can be used as general purpose I/O ports or can be assigned to specific functions (eg clock inputs or status/interrupt outputs) under program control.

More information:

http://dcd.pl/ipcore/785/d2692/

Key features:

Software compatible with SC26C92, SCC2692 and SCN2681 UARTs
Configuration capability
Dual full-duplex independent asynchronous receiver/transmitters
8 character FIFOs for each receiver and transmitter
Programmable data format:
5 to 8 data bits plus parity
Odd, even, no parity or force parity
1, 1.5 or 2 stop bits programmable in 1/16-bit increments
16-bit programmable Counter/Timer
Programmable baud rate for each receiver and transmitter selectable from:
27 fixed rates: 50 to 230.4k baud
Programmable user-defined rates derived from a programmable counter/timer
External 1X or 16X clock
Parity, framing, and overrun error detection
False start bit detection
Line break detection and generation
Programmable channel mode:
Normal (full-duplex)
Automatic echo
Local loopback
Remote loopback
Multidrop mode (also called
‘wake-up’ or ‘9-bit’)
Multi-function 7-bit input port:
Can serve as clock, modem, or control inputs
Change of state detection on four inputs
Multi-function 8-bit output port:
Individual bit set/reset capability
Outputs can be programmed to be status/interrupt signals
FIFO states for DMA and modem interface
Versatile interrupt system:
Single interrupt output with eight maskable interrupting conditions
Output port can be configured to provide a total of up to six separate wire-ORable interrupt out-puts
 Each FIFO can be programmed for four different interrupt levels
Watch dog timer for each receiver
Automatic wake-up mode for multidrop applications
Start-end break interrupt/status
Detects break which originates in the middle of a character
Power down mode
Receiver timeout mode
 

Information about Digital Core Design:

Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and since the early beginning has been considered an expert in IP Core architecture improvements. Thousands of customers became convinced by our unique solutions and billions of people worldwide use our technology in USBs, MP3 players, mobile phones and many other applications.

The innovativeness of DCD's IP solutions has been confirmed by over 500 licenses sold to over 300 customers worldwide, such as: INTEL, SIEMENS, PHILIPS, TOYOTA, OSRAM, GENERAL ELECTRIC, SILICON GRAPHICS, RAFAEL, SAGEM or GOODRICH.

More information: http://dcd.pl/page/147/about/

הפוסט The D2692 UART IP Core offers more הופיע לראשונה ב-Chiportal.

Please click the link below to download the press release from Silicon Labs, SLAB0204 

Download word document here:

http://download.publitek.com/SLAB0204(A)Si50x_CMEMS_Oscillators.docx 

Graphics available here:

http://download.publitek.com/SLAB0204-PR_images.zip 

NEWS RELEASE 

SILICON LABS INTRODUCES THE INDUSTRY’S FIRST SINGLE-DIE MEMS OSCILLATOR 

— New Si50x CMEMS® Oscillators Leap Ahead of Quartz-Based Timing Devices with Superior Frequency Stability, Reliability and Programmability — 

AUSTIN, Texas – June 26, 2013 — Silicon Labs (NASDAQ: SLAB), a leader in high-performance, analog-intensive, mixed-signal ICs, today introduced the industry’s most highly integrated MEMS-based oscillators designed to replace general-purpose crystal oscillators (XOs) in cost-sensitive, low-power and high-volume industrial, embedded and consumer electronics applications such as digital cameras, storage and memory, ATM machines, point-of-sale equipment and multi-function printers. The new Si50x oscillators are based on Silicon Labs’ patented CMEMS® technology – the first to enable MEMS structures to be built directly on top of standard CMOS wafers in high-volume fabs, resulting in fully integrated, highly reliable monolithic “CMOS+MEMS” IC solutions. 

Silicon Labs’ Si50x CMEMS oscillator family achieves smaller size, higher reliability, better aging and higher integration than existing frequency control solutions through a patented monolithic architecture that integrates the MEMS resonator together with the CMOS oscillator circuitry on a single die. The benefits of this unprecedented CMOS+MEMS integration combined with Silicon Labs’ proven mixed-signal expertise are transformational for the frequency control industry: 

•             CMEMS oscillators are manufactured in a high-volume CMOS fab with unified foundry lines that support wafer probing of complete oscillator systems for state-of-the-art quality and process control.

•             CMEMS technology enables guaranteed data sheet performance with 10 years of frequency stability including solder shift, load pulling, VDD variation, operating temperature range, vibration and shock. This guaranteed operating life performance is 10 times longer than typically offered by comparable crystal and MEMS oscillators.

•             CMEMS oscillators tightly couple the MEMS resonator with CMOS temperature sensor and compensation circuitry, ensuring a highly stable frequency output in the face of thermal transients and over the full industrial temperature range. The end result is a predictable, reliable frequency reference over the long operating lifespans of industrial and embedded applications.

•             CMEMS resonators are passively compensated, using materials with offsetting temperature behaviors in the design. This enables Silicon Labs to apply its innovative mixed-signal circuit design expertise to create smaller, lower power and more cost-effective oscillators while ensuring excellent frequency and temperature stability and aging performance. 

The Si50x CMEMS oscillators support any frequency between 32 kHz and 100 MHz. Frequency stability options include ±20, ±30 and ±50 ppm across extended commercial (-20 to 70 oC) and industrial (-40 to 85 oC) operating temperature ranges. The CMEMS oscillators also offer extensive field- and factory-programmable features including low-power and low-period jitter modes, programmable rise/fall times and polarity-configurable output-enable functionality. 

The Si50x CMEMS oscillator family frees customers from supply chain problems that are typical for traditional quartz-based solutions. The Si50x oscillators are manufactured at Semiconductor Manufacturing International Corporation (SMIC), one of the world’s leading semiconductor foundries and the largest, most advanced foundry in mainland China. This strategic foundry relationship increases manufacturing and supply predictability through the benefits of massive scale and quality control. Because CMEMS oscillators are integrated, monolithic ICs, they are packaged in widely produced, molded-compound 4-pin packages, again ensuring a predictable and reliable supply chain. 

“The timing market has reached an inflection point in which the latest-generation MEMS-based oscillators are capable of providing reliable, cost-effective replacements for traditional crystal oscillators,” said Jeremie Bouchaud, director and senior principal analyst, MEMS and Sensors, IHS. “Silicon Labs’ CMEMS technology provides the most integrated crystal replacement solution to date by combining the MEMS resonator and frequency control circuitry into a single-die device optimized for high-volume electronic system designs.” 

Like all Silicon Labs oscillator products, the Si50x oscillators are available for web-based customization with short two week sample lead times or optionally available with “0-day” lead time via instantaneous field programming at the customer’s site by Silicon Labs’ sales channel partners. In addition, the Si50x oscillators are pin- and footprint-compatible with existing quartz or MEMS oscillators, enabling a quick, easy drop-in replacement solution. 

The Si50x family includes four products that enable thousands of flexible timing configurations:

•             Si501 single-frequency oscillator with output-enable (OE) functionality

•             Si502 dual-frequency oscillator with OE and frequency-select (FS) functionality

•             Si503 quad-frequency oscillator with FS technology

•             Si504 fully programmable oscillator supporting all potential configuration features with a 1-pin interface for fine-tuned frequency adjustments measured in parts per billion 

“The Si50x CMEMS oscillator family introduces an important technological step forward in the frequency control market, combining all the manufacturing advantages of a single-die MEMS-based solution while retaining some of the best characteristics of general-purpose crystal oscillators and improving on both reliability and lead times,” said Mike Petrowski, vice president and general manager of Silicon Labs’ timing products. “By leveraging Silicon Labs’ expertise in MEMS design, device and process integration and mixed-signal technology, the Si50x family provides a best-in-class general-purpose oscillator solution for cost- and power-constrained embedded, industrial and consumer electronics applications.” 

Pricing and Availability

Production quantities of Silicon Labs’ Si501/2/3/4 CMEMS oscillators are available now in three industry-standard 4-pin DFN package sizes: 2 mm x 2.5 mm, 2.5 mm x 3.2 mm and 3.2 mm x 5 mm. Pricing for Si50x oscillators in 10,000-unit quantities begins at $0.44 (USD). To ease CMEMS oscillator evaluation and application development, Silicon Labs offers the Si501-2-3-4-EVB Evaluation Kit priced at $99 (USD MSRP), featuring a pre-programmed Si504 device and open sockets in each package size for customer evaluation. 

For more information about Silicon Labs’ Si50x CMEMS oscillator family (including white papers and characterization and qualification reports) and to order samples and development tools, visit www.silabs.com/CMEMS. 

Silicon Labs

Silicon Labs is an industry leader in the innovation of high-performance, analog-intensive, mixed-signal ICs. Developed by a world-class engineering team with unsurpassed expertise in mixed-signal design, Silicon Labs’ diverse portfolio of patented semiconductor solutions offers customers significant advantages in performance, size and power consumption. For more information about Silicon Labs, please visit www.silabs.com. 

Cautionary Language

This press release may contain forward-looking statements based on Silicon Labs’ current expectations. These forward-looking statements involve risks and uncertainties. A number of important factors could cause actual results to differ materially from those in the forward-looking statements. For a discussion of factors that could impact Silicon Labs’ financial results and cause actual results to differ materially from those in the forward-looking statements, please refer to Silicon Labs’ filings with the SEC. Silicon Labs disclaims any intention or obligation to update or revise any forward-looking statements, whether as a result of new information, future events or otherwise.

# # #

Note to editors: CMEMS, Silicon Laboratories, Silicon Labs, the “S” symbol, the Silicon Laboratories logo and the Silicon Labs logo are trademarks of Silicon Laboratories Inc. All other product names noted herein may be trademarks of their respective holders.

CONTACT: Silicon Labs, Dale Weisman +1-512-532-5871, dale.weisman@silabs.com Publitek Technology PR, Oliver Davies +44 1225 470 000, oliver.davies@publitek.com Follow Silicon Labs on Twitter at http://twitter.com/silabs and on Facebook at http://www.facebook.com/siliconlabs.

Explore Silicon Labs’ diverse product portfolio at www.silabs.com/parametric-search.

הפוסט SILICON LABS INTRODUCES THE INDUSTRY’S FIRST SINGLE-DIE MEMS OSCILLATOR הופיע לראשונה ב-Chiportal.

ALISO VIEJO, Calif.—July 30, 2013—Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced the world’s only secure, half-terabyte (TB) solid state drive (SSD) for mobile video surveillance operations, storage area networks (SANs) and other high capacity storage applications requiring superior real-time data protection. The ruggedized TRRUST-Stor Series 200 2.5” SATA SSD operates at sustained 200 megabytes per second (MB/s) and delivers the industry’s fastest full-hardware-based erase time of less than 10 seconds. The self-encrypting, half-terabyte SSD is available now and currently shipping to multiple customers to support applications requiring massive secure storage capacity. 

“Data storage security and reliability are primary defenses in the battle to protect critical information from loss or breach that can put individuals, companies, organizations and nations at high risk,” said Charlie Leader, general manager for Microsemi’s Power Management Group. “Our TRRUST-Stor drives are built for extreme reliability and data integrity, and are the most secure, most reliable SSDs available on the market. We also leveraged our miniaturization technology to create an SSD only 9.5 millimeters in height that meets small form factor parameters required for SANs.” 

The half-terabyte TRRUST-Stor SSD provides military-grade ruggedization as well as unparalleled safeguards and processes for physical data storage with multiple layers of security features. The suite of industry-leading features prevents corruption and unauthorized access with hardware- and software-based barriers. The drive features a built-in compact in-line encryptor with hardware-implemented, NIST-certified AES 256 encryption using the XTS block cipher mode. 

Ruggedization features include superior error correction, 9 petabytes write endurance, power loss protection and more than 2 million hours mean time between failure (MTBF). Enhanced mechanical construction ensures operation in extreme temperatures, humidity, shock and vibration. 

The TRRUST-Stor Series 200 is powered by Microsemi’s second generation Armor processor, enabling robust performance. The Series 200 SSDs also offer the ability to load encryption keys. Customers can input their own AES-256 keys, purge them and reload as needed. Microsemi’s TRRUST-Purge technology destroys keys in less than 30 milliseconds when activated. 

TRRUST-Stor Series 200 Features:

Capacity: Half-terabyte non-volatile storage using reliable, long-life SLC NAND flash

Performance: 200 MB/s sustained reads and writes

Encryption: Hardware-based implementation of AES-256 encryption with XTS, protecting sensitive data

Security: Flexible key management with loadable AES encryption keys. An optional hardware-based authentication enables higher levels of security. The TRRUST-Purge function erases the keys in under 30ms, rendering data forensically unrecoverable.

U.S.-made with full BOM and assembly control

Fast Erase Capability: Hardware-based fast clear of the entire drive occurs in less than 10 seconds

High-reliability: Developed to endure harsh environments, TRRUST-Stor SSD’s ruggedized specifications allow the disk drive to withstand up to 3000 gravitational (G) shock and 30 G root-mean-square acceleration (Grms) of vibration.

Obsolescence Management: Leveraging Microsemi Armor flash management processor and IP, product obsolescence is mitigated.

More information about the TRRUST-Stor products is available at http://www.microsemi.com/solid-state-drives/solid-state-drives. To request a full datasheet, email sales.support@microsemi.com. 

Microsemi has full design, manufacture and test capabilities for a wide variety of multiple chip packages (MCPs), commercial-off-the-shelf (COTS) memory, microprocessors and combination MCPs for demanding applications. These microelectronic products can also be ruggedized and processed for tamper resistance.

About Microsemi

Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance, radiation-hardened and highly reliable analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 3,000 employees globally. Learn more at www.microsemi.com.

Microsemi and the Microsemi logo are registered trademarks or service marks of Microsemi Corporation and/or its affiliates. Third-party trademarks and service marks mentioned herein are the property of their respective owners.

"Safe Harbor" Statement under the Private Securities Litigation Reform Act of 1995: Any statements set forth in this news release that are not entirely historical and factual in nature, including without limitation statements related to its TRRUST-Stor Series 200 SSD, and its potential effects on future business, are forward-looking statements. These forward-looking statements are based on our current expectations and are inherently subject to risks and uncertainties that could cause actual results to differ materially from those expressed in the forward-looking statements. The potential risks and uncertainties include, but are not limited to, such factors as rapidly changing technology and product obsolescence, potential cost increases, variations in customer order preferences, weakness or competitive pricing environment of the marketplace, uncertain demand for and acceptance of the company's products, adverse circumstances in any of our end markets, results of in-process or planned development or marketing and promotional campaigns, difficulties foreseeing future demand, potential non-realization of expected orders or non-realization of backlog, product returns, product liability, and other potential unexpected business and economic conditions or adverse changes in current or expected industry conditions, difficulties and costs of protecting patents and other proprietary rights, inventory obsolescence and difficulties regarding customer qualification of products. In addition to these factors and any other factors mentioned elsewhere in this news release, the reader should refer as well to the factors, uncertainties or risks identified in the company's most recent Form 10-K and all subsequent Form 10-Q reports filed by Microsemi with the SEC. Additional risk factors may be identified from time to time in Microsemi's future filings. The forward-looking statements included in this release speak only as of the date hereof, and Microsemi does not undertake any obligation to update these forward-looking statements to reflect subsequent events or circumstances.

MSCCP 

Source: Microsemi Corporation

הפוסט Microsemi Answers Data Storage Security Threats with World’s Only Self-encrypted, Half-terabyte 2.5” SATA SLC Solid State Drive הופיע לראשונה ב-Chiportal.