The D2692 UART IP Core offers more
The D2692 is a Dual UART Core software compatible with the SC26C92, SCC2692 and SCN2681. But on the contrary to it, DCD’s IP Core offers additional features and deeper FIFOs, like 8 character receiver, 8 character transmit FIFOs, watch dog timer for each receiver, mode register 0, extended baud rate, programmable receiver and transmitter interrupts.
Every receiver is being equipped with fifo to minimize the potential of receiver over-run and to reduce interrupt overhead in interrupt driven systems. Moreover, the D2692 UART IP Core ensures a flow control capability, to disable a remote DUART transmitter, when the receiver buffer is full. To make this design even more functional, there’ve been added multipurpose 7-bit input port and a multipurpose 8-bit output port. They can be used as general purpose I/O ports or can be assigned to specific functions (eg clock inputs or status/interrupt outputs) under program control.
More information:
http://dcd.pl/ipcore/785/d2692/
Key features:
Software compatible with SC26C92, SCC2692 and SCN2681 UARTs
Configuration capability
Dual full-duplex independent asynchronous receiver/transmitters
8 character FIFOs for each receiver and transmitter
Programmable data format:
5 to 8 data bits plus parity
Odd, even, no parity or force parity
1, 1.5 or 2 stop bits programmable in 1/16-bit increments
16-bit programmable Counter/Timer
Programmable baud rate for each receiver and transmitter selectable from:
27 fixed rates: 50 to 230.4k baud
Programmable user-defined rates derived from a programmable counter/timer
External 1X or 16X clock
Parity, framing, and overrun error detection
False start bit detection
Line break detection and generation
Programmable channel mode:
Normal (full-duplex)
Automatic echo
Local loopback
Remote loopback
Multidrop mode (also called
‘wake-up’ or ‘9-bit’)
Multi-function 7-bit input port:
Can serve as clock, modem, or control inputs
Change of state detection on four inputs
Multi-function 8-bit output port:
Individual bit set/reset capability
Outputs can be programmed to be status/interrupt signals
FIFO states for DMA and modem interface
Versatile interrupt system:
Single interrupt output with eight maskable interrupting conditions
Output port can be configured to provide a total of up to six separate wire-ORable interrupt out-puts
Each FIFO can be programmed for four different interrupt levels
Watch dog timer for each receiver
Automatic wake-up mode for multidrop applications
Start-end break interrupt/status
Detects break which originates in the middle of a character
Power down mode
Receiver timeout mode
Information about Digital Core Design:
Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and since the early beginning has been considered an expert in IP Core architecture improvements. Thousands of customers became convinced by our unique solutions and billions of people worldwide use our technology in USBs, MP3 players, mobile phones and many other applications.
The innovativeness of DCD's IP solutions has been confirmed by over 500 licenses sold to over 300 customers worldwide, such as: INTEL, SIEMENS, PHILIPS, TOYOTA, OSRAM, GENERAL ELECTRIC, SILICON GRAPHICS, RAFAEL, SAGEM or GOODRICH.
More information: http://dcd.pl/page/147/about/