Course objectives
Provide Electronic and Computer Engineers with knowledge in basic Logic Design and Verification using Hardware Description Language – Verilog. This can increase productivity and make it easier for engineers to improve the design environment. The course also includes examples and a mini project to be developed by the course participants.
Course organization
The class takes place in Ramat-Gan (Near Tel-Aviv central railway station) once a week, either during working days (between 5.30-10 p.m.) or on Friday (between 9 a.m. – 1.30 p.m.). The course includes 5 meetings and a real design project.
Provide Electronic and Computer Engineers with knowledge in basic Logic Design and Verification using Hardware Description Language – Verilog. This can increase productivity and make it easier for engineers to improve the design environment. The course also includes examples and a mini project to be developed by the course participants.
Course organization
The class takes place in Ramat-Gan (Near Tel-Aviv central railway station) once a week, either during working days (between 5.30-10 p.m.) or on Friday (between 9 a.m. – 1.30 p.m.). The course includes 5 meetings and a real design project.
| מעוניינים לקבל מידע נוסף או פרטים נוספים – השאירו את פרטיכם ונציגנו יחזור אליכם בהקדם |
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