Course objectives
Teach FE FPGA/ASIC Engineers the complete and advanced subjects of the ASIC design flow (Integration, Synthesis, STA, DFT etc…) The course is beneficiary to any FE engineer who wants to learn or strengthen his knowledge in Chip Level Design (Top Level Synthesis, DFT, STA, GLS etc)
Course organization The class takes place in Ramat-Gan (Near Tel-Aviv central railway station) once a week either during working days (between 5-10 p.m.) or on Friday (between 9 a.m. – 2 p.m.). The course is 6 months long and includes a real design project and a graduation exam.
Teach FE FPGA/ASIC Engineers the complete and advanced subjects of the ASIC design flow (Integration, Synthesis, STA, DFT etc…) The course is beneficiary to any FE engineer who wants to learn or strengthen his knowledge in Chip Level Design (Top Level Synthesis, DFT, STA, GLS etc)
Course organization The class takes place in Ramat-Gan (Near Tel-Aviv central railway station) once a week either during working days (between 5-10 p.m.) or on Friday (between 9 a.m. – 2 p.m.). The course is 6 months long and includes a real design project and a graduation exam.
| מעוניינים לקבל מידע נוסף או פרטים נוספים – השאירו את פרטיכם ונציגנו יחזור אליכם בהקדם |
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