Silicon Creations (Georgia, Atlanta) a leader SerDes and PLL provider, has announced new low area and power XAUI (3.125G) SerDes product in TSMC65LP.
This product can be easily ported to any other technology and FAB.
The Silicon Creations 4-lane 1.0Gbps to 3.125Gbps Multi-Rate Serializer/Deserializer) macro includes all high-speed analog functions for 1 to 4 lanes of bi-directional data transport between chips over FR4 and similar PCBs and backplanes.
The SerDes is optimized for low power operation with highly programmable line driver and line receiver. 20b input and output data-paths simplify design of link layers created from RTL using regular standard cells and regular synthesis, place and route flows. Built-in BIST blocks enable stand-alone at-speed self-testing.
Excellent supply noise immunity in the CDR and TX PLLs makes the SerDes ideal for use in noisy mixed signal SoC environments.
Features
• Chip-chip/backplane SerDes with 4 lanes each with data rates of 1.0Gbps to 3.125Gbps.
• Compatible with XAUI and custom back-planes.
• Deemphasize control for line driver compensates for PCB/backplane losses.
• Shared bias and TXPLL common blocks save die area and power.
• Separate Serializer and Deserializer macros simplify assembly of SerDes configurations on single chips or separate chips.
• 20-bit core interface for easy SP&R of Link Layer.
• Comprehensive power-down control.
• Rich testability features including digital test bus and built-in PRBS generation and detection for stand-alone at-speed testing.
• P-S-S-P-G-S-S-G IO plan assures a narrow footprint to minimize IO ring requirements without sacrificing signal integrity.
• Very small die area, significantly less than 1mm2 Rx for 4 lanes, and significantly less than 1mm2 Tx for 4 lanes, including IO cells.
• IO cells and breakers included for ESD-safe drop-in integration in IO ring.
For more information, please contact N.R.G Technologies.
Mobile: +972-54-6640828 Office: +972-72-2330441
E-mail: eli@nrg-technologies.net
