Program Goal
Provide the engineers with knowledge in ASIC physical design: Synthesis and STA. The course can increase productivity and make it easier for engineers to improve their design capabilities. The course also includes real examples and a mini project to be developed by the students. The course for sure will help with job interviews passing and career improving.
Who can attend
Electronics Engineers.
Course duration:
Studies: ~2.5 Months, 1 evening lesson per week.
Classes Schedule
One evening class on weekdays (Mon-Thu, 17:30pm-22.00pm) or Friday (9:30am- 14:00pm)
Class size
20 people max
Course Syllabus
– ASIC Implementation Stage Introduction
– ASIC Technology libraries
– Advanced RTL Design for Synthesis
– STA
– Area/Timing/Power Optimization Methods
– Introduction to TCL
– Synthesis Environment structure + scripts review
– Mini synthesis Project – BI, CRB, FSM etc
– Timing Constraints Definitions
– Synthesis Compilation Reports Analysis
– DFT Stage Introduction + DFT commands in DC syntheis scripts review
– ASIC Ref Project Synthesis Environment Review
– Mini Synthesis Design Review – Block level synthesis, present synthesis reports and analysis
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