Plenary session-3D-IC Designs require 3D tools
Plenary session-The Shift to 3D-IC Structures – Manufacturing and Process Control Challenges
Plenary session-Design of 3D Specific Systems
Track A-New solutions for wireless infrastructure applications:Freescale
Track A-SRAM redundancy insertion:Avnet
Track B-High speed:Marvell
Track C-Designing at 2x:Synopsys
Track D-SoftwareParallelisation & Platform Generation for Heterogeneous Multicore Architectures:Target
Track D-Scheduler performance in many core architecture:Technion
Track D-Living with “Moore”:Sonics
Track E-Challenges in mixed-signal SoCs:Arrow
Track E-clockless_design_language:VLSI Expert
Track E-Contemporary Design of High ADC:IQ analog
Track F-Cost effective centralized adaptive routing for Networks-on-Chip:Technion
Track F-Power Optimization Through Manycore Multiprocessing:ARM
Track F -Algorithmic Memory Increases Memory Performance by an Order of Magnitude:Memoir
Track G-A comprehensive formal verification solution for ARM based SOC design:Jasper
Track G -GPU-Accelerated Verilog Simulations:Rocketick
Track G- Is Advanced Verification for FPGA based Logic needed:Verisense
Track H-Minimizing Customer Returns by Using User- Defined Fault Models:Mentor Graphics
Track H-Evm Test Impairements: Presto Engineering
Track H- The 2012 transition from DFM to PDFD:Intel
