Programmable ICs: the next Innovation Engine

Semiconductor programmable ICs – led by FPGA devices – became immensely successful in recent years, their expanded performance and capabilities match all but the most advanced ASICs and ASSPs. The potential of programmable ICs seems endless; however in 2010 these devices will only capture up to 2% of the global semiconductor market. In order to grow further, the programmable industry must address some fundamental challenges. After reviewing the evolution of FPGAs, these challenges are identified and described. A new programmable framework is proposed to address them and offer the programmable industry an opportunity to compete more aggressively with standard ASSP products. Some concrete steps are then suggested for promoting the further expansion of programmable ICs into new markets. It is argued that this approach will trigger the next wave of innovative semiconductor startups that will be more financially efficient than ever before.

Programmable devices appeared for the first time in the late 1970’s as PAL and PLD devices, which were no more than a matrix of fuses that could implement multi-variable logic functions. Ideal as glue-logic that could be added at a later stage of a hardware design, their popularity soon grew and justified larger devices. The basic architecture changed from a simple fuse matrix to an array of Logic Elements (LE), which themselves evolved from simple collection of 2-input gates to more complex structures. One-time burning of fuses was replaced by electronic re-programming – justifying the term FPGA (Field Programmable Gate Array) that is used to describe this class of devices since the late 1980’s.

Briefly reviewing the history of FPGAs, one can identify several phases in the evolution of these devices. These trends did not start at the same time, but many of them are still at work today, simultaneously with the introduction of yet newer architectural innovations.

As soon as the first programmable devices appeared in the market, the race was on to increase their logic capacity. What started as a few logic gates in the early days of the PLDs has now reached a level equivalent to 20-30 million ASIC gates for the bigger FPGAs. This trend will clearly continue along with Moore’s Law.

The first PLDs were built around a universal fuse matrix that could implement just any logic function of its input variables. Naturally, when more complex circuits were required, the architecture had to evolve too, resulting in a regular array (‘fabric’) of Logic Elements. Initially, these LEs were just an optimized collection of a few logic gates; the combination of many LEs could in principle implement any logic circuit. However, as FPGAs targeted more diverse applications, the need arose to provide more application-specific elements such as memory and DSP blocks (built around adders and multipliers). The fabric had evolved into a combination of elements with several different types. The exact number and mixture of these elements, together with the way they can be interconnected determines the practical capacity of an FPGA.

Having faster, more flexible and higher quantity of inputs/outputs to an FPGA was an obvious result of higher integration and growing bandwidth. However, the expansion in I/O capabilities of FPGAs also introduced a new element which diminished their regularity – the hard-macro. For many I/O circuits, it was no longer possible to use the logic fabric, and dedicated analog and/or digital circuits had to be added to implement some key interfaces (hence the term “hard-macros”). This trend clearly continues today with evermore complex interfaces and higher rates.

The need to integrate on-board micro-controllers led to the introduction of embedded processors into FPGA architectures about a decade ago. Initially, these processors were proprietary and rather simple, but soon enough, more complex industry-standard IP cores were being used. It is still common to find a soft IP core being implemented on FPGA, but for the more advanced processors and interconnects the trend is to use hard-macros that enable much higher performance and lower power. This trend is now at its peak and may allow FPGAs to penetrate new applications in which they could not compete in the past.

Just like most other ICs, the requirement to reduce power (both during active operation as well as during idle cycles) is increasingly important for FPGAs. There are well-known techniques for power reduction and optimization that have been used for several generations of ASIC designs and which are now finding their way to FPGAs. It is expected that this trend will accelerate in the coming years.

The success of FPGAs in recent years is clear for anyone in this industry. A predominant factor in that success has been the long-term economical implication of Moore’s Law – today it is no longer financially feasible to support the development of a standard IC for most of the applications, except those having the highest volume and/or some unique requirements. Therefore, it is no surprise that FPGA design-starts have passed the 100,000 designs/year mark, while the combined design-starts for ASICs and ASSPs plummeted below 8,000 per year. Nevertheless, with all its success and huge potential, the programmable industry will only account for up to 2% of the global semiconductor market in 2010, compared to about 30% for ASICs & ASSPs, combined. The main reason is that the higher volume applications (typically above 100K units per year), where FPGAs are less competitive, account for the majority of the revenues. In order to live up to its promise, the programmable industry will have to overcome some significant challenges.

Although very demanding by itself, it will no longer be sufficient to just follow the integration curve of Moore’s law. If FPGA designers want to promote their devices as a genuine replacement for ASICs and ASSPs, they will need to address an important missing element: Mixed-Signal circuits. With the exception of few PLLs and SerDes circuits, an FPGA cannot implement other analog cells commonly used in modern ICs. Circuits such as ADCs, DACs, RF and Power circuits will have to be added in what may likely become the next trend in FPGA evolution. However, it may not be cost-effective to add mixed-signal cells optimized for a particular application (as done in ASIC/ASSP). What is needed is a configurable implementation of such circuits that could address different variants of the same basic cell, yet not diverge too far from the optimal performance – a tall order which will bring a very high reward for anyone who can deliver it.

The architecture of FPGA devices is becoming more complex and less uniform. Initially, it was based upon purely regular and simple fabric, but as it addressed more demanding applications the picture has changed. First, the LE themselves became more diverse, to the point that the major FPGA vendors offer several product families differing in their mix of cells. Then, special circuits such as clocks, test circuits and other auxiliary functions were added. And finally, the most significant change came with an increasing number and size of hard-macros. The recent addition of advanced processor cores means that the percentage of area devoted to the regular fabric has shrunk considerably. Since not all the hard-macros (or the same combination thereof) are required for all applications, it is no longer effective to offer a single FPGA architecture. The FPGA vendors will have to come up with a creative way of offering several architectures, having a different mix of hard-macros, without losing the manufacturing efficiencies of the classic FPGA platform.

A well-known attribute of an FPGA solution is that it can only effectively address applications with ‘limited’ volume. When volume is below that threshold, it is not cost effective to develop a dedicated IC due to the tremendous costs and risks associated. However, as volume increases, the case for the development of a dedicated IC becomes compelling, since it can offer optimized cost (as well as improved performance and power). Today, this threshold is somewhere around 100,000 units per year. This number is likely to increase with Moore’s law, but it is still ‘below the radar’ for the most popular applications such as wireless and mobile devices, consumer electronics, etc. The major FPGA vendors do have their programs for cost reduction, offering some optimized manufacturing options once quantities increase, but they all fall short of a true answer to the cost pressures typical of higher volume applications. It may not be possible for FPGAs to address all such applications, but in order to significantly improve the current threshold, the FPGA industry will have to offer a more effective route for customization and cost-reduction, while still keeping the added value of flexibility, reduced risk and time-to-market typically associated with programmable devices.

A new Three-Dimensional Framework is proposed to address the challenges raised above. This framework is based upon an anticipated development in semiconductor manufacturing that is expected to enter mainstream usage in 2012-3: 3D IC Stacking. This technique allows connecting and integrating several different ICs in the same package by thousands of parallel signals running vertically through and between the ICs using TSV (Through-Silicon Vias) interfaces. It enables higher integration by connecting several ICs in the same package, and shorter signal traces (i.e., lower power) by running connections vertically ‘through’ the ICs, instead of a much longer routing around them and through separate packages. No less significant is its ability to integrate ICs manufactured with different process technologies.

A typical device in this 3D framework will consist of the following IC layers being stacked above each other in the same package:

·        IC #1: FPGA Fabric

This would include the classic FPGA fabric, but nothing else!

·        IC #2: Application-Specific Baseline IC

This IC will aggregate embedded processor(s), I/O interfaces, and other basic digital hard-macros required for a specific application.

·        IC #3: Mixed-Signal Circuits

This IC will integrate all the mixed-signal circuits required for an application.

Each of these IC layers could be implemented by a single die or several dies (side-by-side or also stacked vertically). Additional IC layers, such as dedicated Memory ICs and other special technologies (e.g., MEMs, sensors, etc.) may be added to this framework. What is clearly needed is some standard TSV interface to connect between these layered ICs.

The 3D framework can provide a solid base to address the challenges facing the programmable industry.

The latest and most advanced digital process technologies, such as 28nm, are far from ideal for many mixed-signal interfaces. By having a separate IC dedicated to the implementation of mixed-signal circuits, it will be possible to use an optimized process technology. It may even be possible to use more than a single mixed-signal IC, using different processes. Offering some clever mixed-signal configurability, as explained above, will still be desirable, but it will be much easier to accomplish when processes optimized for analog performance can be used.

Separating the FPGA fabric from all the hard macros which will be implemented in different ICs allows for a much needed flexibility. The same fabric (or few several fabric families) can be combined with different application-specific ICs. This will enable to separate the effort of developing the fabric from the fixed-style implementation of whatever is implemented today in hard macros. It will be much more efficient to develop new application-specific versions when such application specific baseline ICs can be simply mix-and-matched with pre-existing FPGA fabric ICs and Mixed-Signal ICs.

The current solutions for customization and cost-reduction of FPGAs are clearly lacking. If a conversion from FPGA to ASIC is required, a major effort of RTL design-flow with complicated verification and timing closure is needed, as well as re-engineering (and potentially licensing for a different process technology) of all the hard macros used in the original FPGA device. Having separate ICs for the embedded processors and other hard-macros in a 3D framework will remove the second issue. With only the FPGA fabric IC to convert, a new possibility will emerge – Automatic Conversion from the FPGA gate-level netlist directly to a target standard-cell IC in a flow that will guarantee by-design logic equivalence and adherence to the original timing constraints. Initial steps in this direction are already being taken by some companies.  Following this path, FPGA and EDA companies could offer easy and cost-effective customization of a programmable device, by simply mapping the fabric FPGA IC into a fixed standard-cell IC and then combining it with the other specific ICs used in the original 3D device.  This will create a truly customized device that can compete for performance and cost with ASSPs, while keeping the time-to-market, development cost and risk advantages of programmable devices during the initial phase of market penetration.

While this 3D framework may soon be technically feasible, there is no shortage of challenges. Foundries will have to add new process modules without incurring a high incremental cost. EDA companies will have to add tools to address genuine 3D system partitioning and simulation, as well as dealing with multi-die thermal and mechanical constraints. The design community will have to learn new techniques to effectively take advantage of these new possibilities.

However, complex as these technical issues may be, the business challenges must be addressed as well: There is no single company that can design all the different dies, but there will always be one company that will have to market, sell and support a resulting 3D device. This vendor will have to cope with the responsibility for an integrated device, some parts of which are being provided by other semiconductor suppliers; even if all the dies were to be tested and found to be fully functional as standalone devices, the integrated 3D device may still fail and there should be effective methods to analyze, to correct and to share the costs for solving such problems. It is expected that business alliances will be formed to deal with these issues – the benefits of 3D integration will provide a strong incentive for that. FPGA vendors could be the first to offer such 3D devices as the next generation of their programmable ICs.

This paper presents the 3D framework as a natural evolution for FPGAs, centered on the concept of programmable ICs. However, the resulting framework could also be viewed as the next step in the evolution of embedded ICs. In this embedded centric view, this is the 3D generation of SoC (System-on-a-Chip) devices: It starts with a classic embedded processor SoC and augments it with hardware programmable IC (FPGA) and a Mixed-Signal IC in one 3D package. This could be the background for an interesting battle between the FPGA vendors and some of the traditional ASSP and IDM design houses, each trying to accomplish a similar 3D integration vision. The FPGA vendors may be well positioned to initially lead this new product category. After all, only they can make an FPGA fabric and have the ecosystem of tools, 3rd party IP and worldwide customer support for programmable solutions. However, with the prize being that high, other semiconductor vendors developing processors and embedded ICs may join the race. Some recent steps by Intel may indicate that it is considering such option; it has already formed loose partnerships with Altera (Intel announced an embedded device that integrates two dies: an Atom based IC with an Altera’s FPGA) and Achronix (which was granted access to Intel’s 22nm process technology).

The next Innovation Engine

Perhaps less obvious is the opportunity that the 3D framework may present for semiconductor innovation in general, and fabless start-ups in particular. A common recent concern is the lack of VC funding for new semiconductor startups – it is argued that the fabless start-up model is broken. The reasons were elaborated before in the case for FPGAs – the escalating time and cost it takes to develop an advanced SoC, the shortening product life cycles, and the high risks mean that it is extremely difficult to show a positive return on investment. This can change with the availability of 3D programmable devices: A start-up may take such device with the right combination of existing application IC and mixed-signal IC and innovate just by programming the FPGA layer. In this way it can get to the market much faster and at a fraction of the development cost. The time-to-market may beat any attempt to develop a standard optimized SoC. Once the product is successful, and only then, the startup can commit to customize the FPGA layer and replace it with an optimized standard-cell IC. The resulting device can compete with standard ASSPs, but without incurring the huge initial development costs as before. This strategy could significantly reduce the budget required for a start-up to launch its first product and re-ignite the semiconductor innovation engine again.

The most important step to kick-start this opportunity is to reach some industry standard for 3D interconnect that will facilitate the vertical integration of different ICs. Such standard should cover the architecture, configuration and physical aspects of the interconnect. Some of the requirements such interconnect must include are:

·        Multicore processor interconnect bus (such as the AMBA-4 interconnect family).

·        Flexible interfaces for FPGA that include logic interconnect to the fabric, as well as testing and configuration interfaces.

·        Parallel and serial interfaces to connect with abundant of mixed-signal circuits.

·        Electrical and thermal specifications that enable connection of thousands of signals.

·        Physical dimension and spacing specifications that will allow attaching dies from different process technologies.

The evolution of programmable devices leads naturally to a 3D framework which combines an FPGA with a baseline application IC and a mixed-signal IC in the same package. This integration has significant advantages and will open up exciting opportunities for the programmable industry. It may also put it on a colliding path with embedded SoC vendors who may adapt a similar strategy. The industry will have to agree on some new standards and encourage collaboration between vendors in order for 3D integration to live up to its full potential. Among the benefits of this new approach is the opportunity to transform the cost fundamentals for fabless startups and significantly reduce the budget that is required to develop new competitive products and the time needed to bring them to the market. This may remove some of the financial limitations resulting from Moore’s Law and create a new innovation engine for the semiconductor industry.

Miki Granski, mgranski@hotmail.com